1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Related Art
The technology of producing silicon superintegrated circuits is one of the basic technologies that support the advanced information society in the future. To achieve high-performance integrated circuits, high-performance CMOS devices that are the components of those integrated circuits are essential. Although the scaling rule has been generally applied to high-performance devices, it is becoming difficult to produce higher-performance devices through ultra-miniaturization in recent years, due to various physical limits. One example, there is a problem of interface resistance in source and drain electrode regions.
A typical MOS transistor includes a gate insulating film that is formed on a silicon substrate, a gate electrode that is made of polysilicon formed on the gate insulating film, high-concentration impurity regions that are formed in portions of the silicon substrate located on both sides of the gate electrode and are to be source and drain regions, and extension regions that connect to the high-concentration impurity regions and are formed with an impurity region provided in a portion of the silicon substrate located below the gate electrode. Further, a silicide film is provided on the gate electrode and the high-concentration impurity regions.
The silicide film provided on the high-concentration impurity regions forms a Schottky junction between each high-concentration impurity region and each corresponding extension region. The resistance on the drain side is divided into the resistance of the silicide film (Rsh), the resistance of the drain region (Rd) caused by the bulk film, and the interface resistance of the Schottky junction (Rc). Among the three resistances, the interface resistance is generally known to be the highest. Since the interface resistance does not decrease according to the scaling rule, to reduce the interface resistance poses a very important problem in improving the performances of MOS transistors in the future.
Of the Schottky junctions formed between the silicide film and the high-concentration impurity regions, as to the Schottky junction on the drain side, electrons that have reached the high-concentration impurity region tunnel through the Schottky barrier height, towards the silicide film. The easiness of electron tunneling is generally referred to as the tunnel probability. The higher the tunnel probability is through a junction, the lower the interface resistance is. The tunnel probability is known to exponentially decrease in relation to the product of the Schottky barrier height and the tunnel distance. Therefore, the Schottky barrier height and the tunnel distance should be effectively reduced, so as to reduce the interface resistance.
One of the methods to do so involves segregating high-concentration activated impurities on the silicon side at the interface between the silicide film and the silicon film (see R. L. Thornton, Elec. Lett., 17, 485 (1981), and A. Kinoshita, SSDM, A-5-1 (2004), for example). Here, it is preferable to segregate the high-concentration activated impurities in a narrower range from the interface. Such an interface has the effect of improving the mirror effect and enhancing the bending of the silicon conduction band, so as to dramatically reduce the Schottky barrier height and the tunnel distance. However, such an interface has not yet been produced to this day.
The processing technique for forming a metal silicide on the gate electrode and the source and drain regions in a self-aligning fashion is called the SALICIDE (Self-aligned Silicide) process technique, which is an important technique for reducing the resistance in the gate electrode and the source and drain regions in a CMOS device.
Conventionally, disilicides such as TiSi2 and CoSi2 having low resistance among low-thermal metal silicides have been used for CMOS devices. However, in the trend of ultra-miniaturization of devices, the use of nickel monosilicide (NiSi) that has low sheet resistance and consumes less silicon (Si) in the silicidation process is expected for next-generation CMOS devices.
In the SALICIDE process, NiSi is considered to be beneficial, as it requires a lower processing temperature than the currently used CoSi2. Generally, nickel silicide has many phases. The phase of nickel silicide that is formed at a lowest annealing temperature is dinickel silicide (Ni2Si). As the annealing temperature rises, it changes to nickel monosilicide (NiSi), and to nickel disilicide (NiSi2). According to the conventional nickel SALICIDE process, nickel monosilicide (NiSi) is formed at last, as it has the lowest resistance. More specifically, after a Ni film is formed on a silicon film, annealing is performed at 350° C. for 30 seconds, to form dinickel silicide (Ni2Si). Annealing is then performed at 500° C. for 30 seconds, to change the dinickel silicide (Ni2Si) into nickel monosilicide (NiSi).
To reduce the interface resistance at the interface between the nickel silicide film and the silicon film poses one of the most crucial problems with the nickel SALICIDE process that is expected to be put into practical use for next-generation CMOS devices by the scaling rule.
In a sample that is formed with two silicon films into which typical impurities, arsenic (As) and boron (B), are introduced, a silicide film is formed by the conventional nickel SALICIDE process, and the interface between the nickel monosilicide (NiSi) and the silicon (Si) film is observed through back-side SIMS (Secondary Ion Mass Spectroscopy). The results of the observation show that arsenic (As) is distributed on both sides of the interface, but most of boron (B) is distributed in the NiSi film. Therefore, a decrease in Schottky barrier height cannot be expected in the high-concentration impurity region (a p-type silicon layer) doped with boron (B). The results of actual experiments of current-voltage characteristics also show that an effective decrease in Schottky barrier height can hardly be seen.